The subject matter of this application is related to the subject matter in a co-pending non-provisional application by the same inventor(s) as the instant application and filed on the same day as the instant application entitled, xe2x80x9cApparatus for Flexibly Allocating Request/Grant Pins Between Multiple Bus Controllers,xe2x80x9d having Ser. No. 09/418,465, and filing date Oct. 15, 1999.
1. Field of the Invention
The present invention relates to buses in computer systems. More particularly, the present invention relates to a system for flexibly allocating I/O pins used for bus request and bus grant signals between multiple bus controllers located on the same semiconductor chip.
2. Related Art
Much of the interconnection circuitry in a microprocessor-based computer system is typically aggregated in a xe2x80x9ccore logicxe2x80x9d unit that couples the microprocessor to other parts of the computer system, such as a memory, a peripheral bus and a graphics controller. For reasons of cost, it is preferable to integrate the core logic unit into a single semiconductor chip. However, the I/O pin limitations on a single chip can present problems. For example, a single core logic chip that includes all of a computer system""s interconnection circuitry may require interfaces for a processor bus, a memory bus, an AGP bus for a graphics controller and a PCI bus for peripheral devices. Providing I/O pins for all of these interfaces requires many hundreds of I/O pins, especially if the buses support 64 bit transfers. Given present semiconductor packaging technology, this I/O pin requirement can easily exceed the I/O pin limitations of a single semiconductor chip.
Note that many bus signals lines are not utilized well. In particular, some bus grant lines and bus request lines are not always needed. Recall that bus request lines are used by devices on the bus to request control of the bus from a bus arbiter in order to perform bus accesses. Bus grant lines are used by the bus arbiter to grant control of the bus to a requester. In a typical bus, such as the peripheral component interconnect (PCI) bus, there is one request line and one grant line for each master device on the bus. For example, the PCI bus supports up to seven bus request lines and seven bus grant lines for up to seven bus masters.
In order to conserve on the number of I/O pins used, a typical core logic chip provides a limited number of pins for request lines and grant lines. This limits the number of bus master devices that can be supported. Furthermore, the number of request and grant lines are typically fixed for each bus controller. This means that a typical core logic chip cannot be used in certain computer system configurations. For example, a given computer system configuration may require a particular allocation of request and grant lines between bus interfaces, whereas another computer system configuration may require a different allocation.
What is needed is a system for flexibly allocating I/O pins used for bus request and bus grant signals between multiple bus controllers located on the same semiconductor chip.
One embodiment of the present invention provides a method for flexibly allocating I/O pins used for bus grant signals between bus controllers located on a semiconductor chip. The method operates by receiving a first set of grant lines from a first bus arbitration circuit. This first set of grant lines is used to grant control of a first bus to devices on the first bus. The method divides the first set of grant lines into a first subset of grant lines and a second subset of grant lines. The method also receives a second set of grant lines from a second bus arbitration circuit. This second set of grant lines is used to grant control of a second bus to devices on the second bus. The method divides the second set of grant lines into a third subset of grant lines and a fourth subset of grant lines. Next, the method selects outputs from between the first subset of grant lines and the third subset of grant lines, and drives the outputs off of the semiconductor chip through a first set of output pins. During a first mode of operation, the first subset of grant lines is selected to be driven through the first set of output pins, and during a second mode of operation the third subset of grant lines is selected to driven through the first set of output pins.
In one embodiment of the present invention, the method additionally drives the second subset of grant lines off of the semiconductor chip through a second set of output pins, and also drives the fourth subset of grant lines off of the semiconductor chip through a third set of output pins.
In one embodiment of the present invention, the method receives a set of request lines from input pins of the semiconductor chip. The method divides the set of request lines into a first subset of request lines, a second subset of request lines and a third subset of request lines. The method routes the first subset of request lines to the first bus arbitration circuit; routes the second subset of request lines to the second bus arbitration circuit; and routes the third subset of request lines to the first bus arbitration circuit and the second bus arbitration circuit.
In a variation on this embodiment, routing the third subset of request lines includes selectively routing the third subset of request lines to either the first bus arbitration circuit or the second bus arbitration circuit. During the first mode of operation the third subset of request lines is routed to the first bus arbitration circuit, and during the second mode of operation the third subset of request lines is routed to the second bus arbitration circuit.
In one embodiment of the present invention, the method accesses a configuration register that indicates whether the selector circuit is operating in the first mode of operation or in the second mode of operation.